1. Technical Field
The present invention relates to a semiconductor device, and, particularly, to a semiconductor device including a fuse element.
2. Related Art
In order to avoid yield reduction caused by a micro fabrication and density growth of semiconductor device, the semiconductor device has been designed to allow modification of a circuit, and switching between redundant circuits after a testing process by using a fuse circuit. As one example, a fuse element is cut by melting and evaporating caused by laser light irradiated through an opening for fuse cut on the fuse element. In the opening for fuse cut, an insulating film covering over the fuse element is thinner than other portions. Moreover, the insulating film in the portion, in which the fuse element is cut, is blown off when melting and evaporating the fuse and the fuse element is exposed. As described above, a distance between the surface of the semiconductor device and the fuse element in an insulating interlayer is smaller, or the fuse element is exposed at the surface in the portion, in which the fuse element is cut. Thereby, when the surface of the semiconductor device is electrically charged at, for example, an assembly process of the semiconductor device, electrostatic discharge easily occurs toward the fuse interconnect to cause damage of the fuse element itself, or damage by electrostatic discharge of, for example, a gate insulating film of an internal circuit connected to the fuse element. Accordingly, the reliability will be lowered.
Conventionally, there has been a problem that, when a fuse formed on a semiconductor substrate is cut by ion beam, a charged particle is irradiated onto the semiconductor device to cause charging of the semiconductor, by which an insulating film is damaged to cause failure of the semiconductor device. In order to solve the above problem, Japanese Laid-Open Patent Publication No. H02 (1990)-244740 has disclosed a semiconductor device in which at least two pn junctions are formed at a distance from each other at a position near an interconnect to be cut by ion beam, and the two pn junctions and the interconnect to be cut are electrically connected to each other.
FIG. 7 is a cross sectional view showing a configuration of the above semiconductor device. A fuse interconnect 3 as an interconnect to be cut is connected to n-type impurity diffusion layers 4 through contacts 6a and 6b at the both ends of a fuse portion to be cut 2. Here, the impurity diffusion layers 4 are isolated by element isolation insulating films 11. The impurity diffusion layers 4 forms a pn junction with a p-type semiconductor substrate 9. In the above configuration, when an ion beam is irradiated from above an insulating interlayer 8 onto the fuse to be cut 2 of the fuse interconnect 3 to increase the electric potential of the fuse interconnect 3, non-destructive breakdown of the two pn junctions is caused, and electric charges charged on the fuse interconnect 3 are discharged to the p-type semiconductor substrate 9. Thereby, charging of the semiconductor device may be prevented to avoid damage of the insulating film.
Japanese Laid-Open Patent Publication No. 2006-073937 has disclosed a semiconductor device including: a semiconductor substrate doped with first conductive-type impurities; an insulating film formed on the surface of the semiconductor substrate; a fuse formed on the insulating film; a first diffusion layer electrically connected to the fuse and formed on the surface of the semiconductor substrate by doping second conductive-type impurities; a second diffusion layer, which is connected to the substrate potential, which is formed on the surface of the above semiconductor substrate by doping the first conductive-type impurities to higher concentration than the first impurities doped to the semiconductor substrate, and which forms a diode together with the first diffusion layer and the semiconductor substrate; and a transistor electrically connected to the first diffusion layer. With this configuration, it is assumed to be possible to protect the transistor in an internal circuit from ESD surges generated on the cut surface of a redundant fuse of the semiconductor device.
Japanese Laid-Open Patent Publication No. H01 (1989)-081341 and Japanese Laid-Open Patent Publication No. H02 (1990)-033949 have disclosed a semiconductor device with a configuration in which an interconnect, connecting a fuse and an element in an internal electronic circuit and the like, is divided into two pieces and the pieces are connected to each another through a diffusion layer. With this configuration, even when the interconnect connected to the fuse is corroded by water intrusion and the like, the interconnect connected to the element in an internal electronic circuit and the like may be prevented from being corroded.
Japanese Laid-Open Patent Publication No. H07 (1995)-078872 has disclosed a technique which inhibits corrosion advancement of a metal interconnect by providing a connecting unit made of a conductive non-metallic material between a metal interconnect as a fuse and a node.
Conventionally, there has been a problem that, when a protection element is provided in order to protect a transistor in an internal circuit from ESD (Electro-Static Discharge) surges, as described in Japanese Laid-Open Patent Publication No. H02 (1990)-244740, and Japanese Laid-Open Patent Publication No. 2006-73937, a utilized area for arranging the protection element is increased.